1. Field of the Invention
This invention relates to the field of integrated circuit storage of analog signal samples and multi-level digital signals in a memory array.
2. Prior Art
Up to the present time, nonvolatile analog storage in integrated circuits has been performed predominantly in EEPROM memory cells that utilize Fowler-Nordheim electron tunneling for both erase and program modes. These cells are usually constructed of a MOS transistor with an intermediate polysilicon gate positioned between the channel and an upper polysilicon control gate. The intermediate polysilicon gate does not have any ohmic electrical connections, is completely surrounded by an insulator and is commonly termed the floating gate. Electrical charge is added to or subtracted from the floating gate by applying voltages to the four available terminals of the transistor (source, drain, gate and substrate) such that electric fields are imposed across a particular region of the dielectric surrounding the floating gate, generally called the tunnel oxide. By correct three dimensional design of the cell, and by correct selection of applied voltages, the fields across the tunnel oxide are sufficiently high to induce electron tunneling through the dielectric. The addition or removal of electrons to or from the floating gate causes the threshold of the transistor, as measured by applying a voltage to the upper control gate, to be modified. Assuming NMOS transistors are used, the direction of the high electric field determines whether electrons tunnel onto or off the floating gate and therefore determines whether the resulting change in threshold voltage is an increase or a decrease, respectively.
There are many examples of floating gate digital memories, whereby the threshold voltage of the floating gate transistor is changed by significant amounts, in the order of a few volts. One logic state is represented by a wide range of thresholds and the other logic state(s) is represented by a different range(s) of thresholds. Information is read from the cell generally by determining whether the transistor conducts or does not conduct when the transistor is biased into a predetermined read condition. Analog storage, on the other hand, requires that small or continuous changes be made to the threshold of the floating gate transistor, and requires that the reading of the transistor give a determination of an actual voltage from the transistor, or an indication of how conductive the transistor is. Examples of analog storage can be found in U.S. Pat. Nos. 4,627,027 (Rai), 4,890,259 (Simko), 4,989,179 (Simko), 5,220,531 (Blyth), 5,241,494 (Blyth), and 5,294,819 (Simko).
The technique utilized in U.S. Pat. No. 4,627,027 relies on a programming voltage applied through a high value resistor to the drain of the floating gate transistor such that the transistor starts to conduct when the floating gate is charged sufficiently high, relative to an applied analog level on its source. At the onset of conduction the drain current causes an increasing voltage drop across the resistor and therefore reduces the programming voltage applied to the drain. Tunnel current therefore reduces and the floating gate reaches a level which has a close relationship to the input voltage on the source.
U.S. Pat. No. 4,890,259 and U.S. Pat. No. 4,989,179 describe a non-volatile memory array of cells into which analog or multi-level signals are stored by continuously sampling the signal and sequentially temporarily storing the samples in a set of sample and hold circuits. The parallel outputs from the sample and hold circuits are then used to control an iterative write sequence for an equal number of memory cells, the iterative write sequence being independent for each of the cells as controlled by the respective sample and hold output. The iterative write sequence is a series of write programming voltage pulses, each followed by a read operation, wherein the programming voltage pulses increase in amplitude until the voltage level read from the cell matches the desired analog level from the corresponding sample and hold circuit, at which time the series of programming pulses for that cell is terminated. U.S. Pat. No. 5,220,531 and U.S. Pat. No. 5,241,494 are improved methods and apparatus for iterative analog storage that allow improved performance and manufacturability. U.S. Pat. No. 5,294,819 is a method for analog storage in an EEPROM cell containing a single transistor. A common characteristic of the aforementioned examples is the use of an EEPROM cell that uses Fowler-Nordheim tunneling for both erase and program modes of operation.
Another class of non-volatile memories relies on hot-electron injection for the program operation. Erasure may be performed by exposing the surface of the integrated circuit to Ultra Violet light, or alternatively may be performed electrically by Fowler-Nordheim tunneling. In either case the program function is performed by hot electron injection, whereby the floating gate transistor of the selected cell is biased such that electrons in the source to drain channel are subjected to high electric fields. The energy imparted to the electrons is sufficiently high for electrons to jump the energy gap of the oxide layer and terminate on the floating gate. The proportion of electrons terminating on the floating gate depends on the particular bias conditions, one of which is the floating gate voltage and therefore the field across the oxide under the floating gate. Generally speaking, high source currents are required to supply sufficient charge transport to program an adequate threshold change in a reasonable time period i.e. a few volts in a few tens or hundreds of .mu.sec. Transfer efficiency is therefore very low; in the order of 1 electron which terminates on the floating gate for 10.sup.6 or 10.sup.7 channel electrons. Since programming requires high currents and high voltages, the techniques used for on-chip voltage multiplication from a single power source such as those found on EEPROM devices are not practical, and it becomes necessary to use external power sources to supply the program current. A special external supply, capable of relatively high power, is a significant disadvantage. Some recent improvements, however, have overcome some of these difficulties. One example is described in U.S. Pat. Nos. 5,029,130, 5,067,108 and 5,289,411 --an improved technique for hot electron injection, whereby the programming transfer efficiency is much improved, and on-chip voltage multiplication becomes practical. While the above patents disclose the manufacture of the improved device and its operation and use for digital data, the present invention relates in the preferred embodiment to storage of analog data, and also introduces different techniques for writing to and reading from the cell. This invention can also be applied to other types of non-volatile cells that use hot electron injection. In addition, while the present invention uses sample and hold circuits and iterative programming techniques similar to those disclosed in U.S. Pat. Nos. 4,890,259, 4,989,179 and 5,241,494, there are significant differences from these patents. Briefly, the program control is performed by switching current instead of voltage, as well as significant architectural differences in the writing circuits.